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Text File | 1995-04-09 | 15.8 KB | 392 lines

NAME make - The SozobonX make SYNOPSIS make [options] [<macro>=<val>] ... [<target> ...] ld [-Vvheiknpqrst] [-]|[-f <makefile>] [-c|C <dir>] [-L <size>] [<macro>=<val>] ... [<target> ...] You have to keep this order in comandline: first the switches, then macro assignements and at last the targets! DESCRIPTION make is a tool to build one or more files from other files using rules describing the commands how to make a file from another. Therefore dependencies are listed in a makefile and in builtin rules so that make knows which time-stamps of wich files it has to compare. This manual describes all features and options from Sozobon make. It is not a description of how to use make and writing makefiles. If you are not familiar with make read a general make documentation like the 'make.doc' from this distribution or the GNU make manual. The makefile make looks at first for a makefile named 'MAKEFILE', or 'Makefile', or 'makefile', if there is none specified in the commandline. This file has to be in cwd. make will attempt to use its internal rules if no makefile exists, but a target was given on the command line. This means that simple programs in a single file can be made without a makefile by typing: make file.ttp include With the include directive the reading of current makefile is stopped, all specified files are processed like the default makefile , and after that the curent makefile processing is continued. Default targets are never taken from an include file! include <file> [<file> ...] <file> may be a macro, known at this state, and have wildcards. Include files are searched like the ones in $MAKEFILES. line continuation The line continuation character is '\'. Back slashes may appear in pathname, but NOT at the end of a line, as it will be taken as a continuation backslash, and not as a part of the pathname. This should not create any big problem as far as i can see - just add a space at and of line. Rules If for a target with an extension (!!) no commands are specified, make tries to find an implicit rule that matches this target by testing possible dependencies. The assumed dependency is added to the target's dependency list, if it exists. If not, the extension of the assumed dependancy is compared with the first depandancy of the target, if it's the same the matching implicit rule will be used for this target. To pervent a problem with linking all dependencies (default rule) and im- plicit adding an assumed target, this not added for the default target (if there are any dependencies). So: foo.ttp: bar.o x.o y.o will run the linker with the commandline: cc -o foo.ttp bar.o x.o y.o And not add any dependency 'foo.o'. The imlicit rule used is: .o.ttp: $(CC) $(LDFLAGS) -o $@ $^ $(LOADLIBES) The implicit rule used for a default target is searched by look- ing at the first dependency's suffix too! Think of this if you specify dependencies with different suffixes! For the default target you will have to write your own command(s) in this case. The implicit rules are always suffix rules. So your targets and dependencies must have a suffix form '.SUFFFIXES' if they should be made with an implicit rule. You can of course define new implicit rules, or overwrite built-in ones. Don't forget to add the new suffixes to '.SUFFIXES'! The most important builtin rules are: (you can see all with option -p.) .c.o: $(CC) -c $(CFLAGS) $< .s.o: $(CC) -c $(CFLAGS) $< .c.ttp: $(CC) $(CFLAGS) $(LDFLAGS) -o $@ $< $(LOADLIBES) .o.ttp: $(CC) $(LDFLAGS) -o $@ $^ $(LOADLIBES) .s.ttp: $(CC) $(CFLAGS) $(LDFLAGS) -o $@ $< $(LOADLIBES) .l.c: $(LEX) $(LFLAGS) $< .y.c: $(YACC) $(YFLAGS) $< Macros Macros are normally set in the following order: internal defaults environment variables EXPORTED makefile assignments commandline assignements EXPORTED If the -e assignments in the makefile and the order becomes: internal defaults makefile assignments environment variables EXPORTED commandline assignements EXPORTED Internal (predefined) macros are: PATH = \usr\bin,\bin SHPREFIX = -c CC = cc AR = ar TEX = tex LEX = lex YACC = yacc CFLAGS = LDFLAGS = LOADLIBES = TFLAGS = ARFLAGS = MAKE = make MAKEFLAGS = The macros $(MAKE) and $(MAKEFLAGS) are set to the values, make was invoked with. The -c and the -f switch with their arguments are of course not inherited into macro $(MAKEFLAGS). Both are not exported by default, but maybe used to run nested makefiles and, if you want so, keeping the options the first make was started with. The syntax for recognizing a macro/variable is: $(VAR) or ${VAR}, where 'VAR' is the variable/macro name. To define a variable/macro in a makefile write: '<macro> = <value>' where the rest of the line gets the value, skipping leading and trail- ing whitespaces. A macro/variable is evaluted immediately when found while read- ing the makefile, if it is part of another variable's value, a target, a dependency or any statement's argument. It is evaluated when used, if it is in a commandline in a rule, or in a commandline for an explicit target. Special variables with the syntax %(VAR) or %{VAR} are only allowed in dependency lists. These variables make it easier e.g. to add a dependency build from the name of the target but without the path part there: $(OBJECTS): %(*F).c $(HEADERS) cc -o $(*).o $(*F).c This is expanded for every target in $(OBJECTS) to: <pathtarget.suffix>: <target>.c 1.h 2.h .. cc -o pathtarget.o target.c builtins export Global export: Export all macros from makefiles via en- vironment to subsequent processes (nested makes, or other child processes). this directive works only if no unexport follows export <macro> ... Export all specified macros as environment variables, they must not exist until this directive is read, a global un- export does not affect this directive. export <macro> = <value> Defines a macro and makes it exportable at same time. Exported macros are expanded before putting them into environment! In a subsequent make you can use them as macros again. unexport Don't export any macros from any makefile; this is default, and resets only a earlier global export directive (from another included makefile perhaps); the last export or unexport directive is valid unexport <macro> ... Do not export the specified macros, even environment vari- ables or commandline assignements are affected; a global export directive does not change the macros' status. unexport <macro> = <value> Define a macro and make it private (usefull if it was an environment variable). override <macro> = value Define a macro and prevent it from being overwritten; sub- sequent assignements to this macro (e.g. from commandline) will not replace the current value, but be appended to the end. Phony (special) Targets .SUFFIXES The list of dependecies, recognized by make. .PRECIOUS Dependencies of .PRECIOUS are not deleted if a command fails, by default it has no dependencies. .IGNORE Sets a global switch like -i (ignore). .SILENT Sets a global switch like -s (silent). .STRIPPATH The path part of every target's name is stripped when making the implicit dependency. This makes it easier to compile objects from a sourcecode for different program versions into diffferent directories. This is some sort of a global %(*F) for all inplicit dependencies. .SHELL Sets a global switch: all commandlines are passed to the shell $SHELL. Commandline Prefixes You can prefix each commandline in the makefile with one or more of the following prefix chars. The '@' and '-' prefixes must be first ones, the excluding '%' and '!' may follow. These prefixes modify the commandline handling. @ Sets the silent switch to this single comandline. - Sets the ignore switch to this single comandline. ! By default this make executes all commandlines by self. This prefix makes make to pass this single commandline to a shell. This is an important feature, cause make performs no expansions than wildcard expansion on the commandlines. % Forces make to treat the command in this line as an builtin one. Automatic variables $@ Is the current target of an implicit rule, or an ex- plicit one with multiple targets. $(@F) is the filename part of $@ , and $(@D) the path in $@. $* This the basename of the curent target. This works only if the target has a recognized suffix. $(*F) is the filename part of $* , and $(*D) the path in $* $< This is the name of the first dependency. If the target got it's commands from an implicit rule, this will be the first dependency added by this rule. $(<F) is the filename part of $< , and $(<D) the path in $< $^ This macro contains the names of all dependencies, with spaces between them. This is useful for linking a file. (See default rules). $? The names of all dependencies that are newer than the target, with spaces between them. This maybe useful in explicit rules when you want to work only with the changed files. For example to update an archive: Wildcards This make tries to expand every token containing a wildcard character like: '*' or '?' or '[' as a filename. The token is replaced by the matching filenames found. It uses usual FNRexpressions as wildcards: '*' '?' '[...]' '[?-?]' '[^...]' OPTIONS --version -V Print detailed Version information to stdout and exit --help -h Print the help page and exit -v (verbose) Generally show more information about what make is doing and print short version information (to stderr). - Read the makefile from stdin. -c <dir> (cd) Change the current working directory to <dir> before run- ning (and looking for a makefile). -f <file> (file) Use and read file <file> as makefile. -L <size> (line) Set the internal buffer size for reading and expand lines from a makefile to <size> KBytes. Default size is 4K, you line too long or a similiar one. -e (env) The environment variables overwrite the makefile's variables. -s (silent) Don't print anything except error messages. -i (ignore) Ignore the exit status of the commands excuted by make: just execute all comands. -k (keep) Keep going on processing the makefile after an error. This is much better than -i cause the next target will be made after an error until make can't do anything more. -n Do nothing, just tell what make would do (e.g. for testing makefiles). -q (question) Do nothing but test the target. If it is not up to date make will return a status of 1. -t (touch) Don't really make any targets, but touch the files which need an update. ENVIRONMENT The environment is read and macros corresponding to the vari- ables found are initialized within make. This means that set- ting the variable $PATH causes make to set the macro PATH to the value found and use that for command searches as described above. With a macro assignement in commandline you can over- write any macro, from makefile and environment, too. If a environment variable '$MAKEFILES' exists, it's value is used as a list of makefiles to include. The default target is never taken from one of these files, but they are read at first. If there are no absolut paths specified in the filenames, they are searched in the paths of '$INCLUDEDIR' and a directory 'make' in that path. If there is no environment vari- able '$INCLUDEDIR' or '$INCLUDE' (a list of inlude paths) '\usr\include,\usr\local\include' is assumed. $INCLUDEDIR This path replaces the builtin search pathes for include makefiles not to find in cwd. $INCLDUE A list of pathes where makefiles to incldue are searched. If $STDERR is present, stderr handle (2) is used for diagnostic output. DIAGNOSTICS make will claim about a missing target, if there is none in commandline or the makefile. If it finds a syntax error in the makefile it will report this and exit. SEE ALSO cc(1) BUGS Without doubt, there are some bugs in this program. If you discover one, please report it to maintainer. AUTHOR PD make Adapted from mod.sources Vol 7 Issue 71, 1986-12-03. port to ATARI TOS by Jwahar Bammi & Ton van Overbeek adapted for SOZOBON by Tony Andrews 1988 eXtended Version by Jerry G Geiger (1992-1995) VERSION make V2.04 Mar 30 1995